1. Field of the Invention
The present invention generally relates to a chip packaging technology for semiconductor IC, and more particularly, to a leadframe type package technology.
2. Description of Related Art
In terms of leadframe type package, it is usual to utilize a multiple wire structure to establish leads with low inductance for a power net. A lower inductance is advantageous to reduce power bounce, and thereby to reduce noise coupling whatever passing through the above-mentioned power net or sourced from the power net.
FIG. 1 illustrates a conventional triple conductive wires structure used in a leadframe type package. Referring to FIG. 1, three conductive wires 20 respectively connected to each of three chip pads 10 are together connected to the same lead 30 so as to produce a parallel effect and thereby reduce the parasitic inductance. In some designs of the structures similar to the above-mentioned one for meeting the demand on a less inductance, more than three conductive wires, that is, four or more than four conductive wires 20, may be chosen in the designs.
For a conductive wire made of gold with a small section and a horizontal length of 1 mm, the roughly estimated inductance thereof is 1 nH. The inductance occurred on a power net would cause power bounce during switching signals. In particular, the faster switching the signals and the larger the inductance of the power net, the more serious the power bounce effect is. Since the above-mentioned conductive wires are in parallel connection and the parallel connection results in a lower parasitic inductance, so that the above-mentioned multiple wire structure is preferred.
However, the above-mentioned conductive wires must be connected to the same lead, which means the distances between the conductive wires are unable to be increased and, in turn, the mutual inductance between the lines would be relatively increased. The total inductance of a power net is composed of both self inductance and mutual inductance. As a result, the lower self inductance produced by the parallel connection and the increased mutual inductance would limit the total inductance of the multiple wire structure from being reduced to the design requirement.